Memory circuit with sense amplifier

ABSTRACT

A memory has a pre-amplifier for generating an output signal and a reference signal. The memory includes a comparator for comparing the output signal to the reference signal. The comparator includes a bias stage for generating a bias signal, wherein the bias signal is an average of the output signal and the reference signal. The comparator further includes a first output stage for generating a first comparator output signal by comparing the output signal and the bias signal. The comparator further includes a second output stage for generating a second comparator output signal by comparing the reference signal and the bias signal.

FIELD OF THE INVENTION

This invention relates to memory circuits, and more particularly, tosensing the logic state of memory cells in a memory circuit.

BACKGROUND OF THE INVENTION

In memories, a continuing desire is increased speed, which primarily islimited by the read operation in which sensing of the logic state ofmemory cells is performed. Typical issues are amplification and timing.It is important to only begin sensing when the signal being sensed issufficiently developed. But due to difficulties in manufacturing inproviding perfectly matched transistors, amplification of the signal canbegin in the wrong direction early in the signal development stage. Anywaiting for signal development adds to the read time, which isundesirable. This tension between waiting to ensure sufficient signaldevelopment and early sensing for fast read times is generally presentin the design of a memory. Thus, any improvements in the ability tobegin the sensing as early as possible while avoiding beginning sensingwhen the signal being sensed is not sufficiently developed is desirable.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and further and more specific objects and advantages ofthe invention will become readily apparent to those skilled in the artfrom the following detailed description of a preferred embodimentthereof taken in conjunction with the following drawing:

The sole FIGURE is a combination circuit diagram and block diagram of amemory according to an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

In one aspect, a memory has a sense amplifier that has a comparator forcomparing a reference voltage and bit signal, which is the signal beingsent and further has a bias circuit. The bias circuit generates a biasvoltage that is based on a combination of the bit signal and a referencevoltage. By using the combination for the bias voltage, the comparatoris able to avoid amplifying in the wrong direction at the beginning ofsensing. This is better understood by reference to the drawings and thefollowing description.

Shown in the FIGURE is a memory circuit 10 comprising a memory array 12and a sense amplifier 14. Sense amplifier 14 comprises a preamplifier 16coupled to memory array 12, a comparator 18 coupled to preamplifier 16,and a latch 19 coupled to comparator 18. In the FIGURE only memory cells20, 22, and 24 are shown for memory array 12 but many more cells arepresent but not shown. Memory cell 20 depicts a memory cell that hasbeen selected for sensing. Memory cells 22 and 24 are reference cells;one being a logic high and the other a logic low. Array 12 in thisexample is a magnetoresistive random access memory (MRAM) but could beanother memory type such as, for example, a floating gate memory, a readonly memory, or a dynamic random access memory. Many features of amemory that are well known in the art, such as decoders, addressbuffers, and write circuitry, are not shown in the FIGURE.

Preamplifier 16 provides a first stage of amplifying. Preamplifier 16provides a bit signal Vbit based on memory cell 20, and a referencevoltage Vref based on the combination of memory cells 22 and 24. Intypical fashion, bit signal Vbit and reference voltage Vref becomeactive in response to a clock signal.

Comparator 18 comprises P channel transistors 26, 28, 36, and 40; Nchannel transistors 30, 32, 38, and 42; and transmission gates 44, 46,and 48. Transistor 26 has a gate for receiving bit signal Vbit, a sourceconnected to a positive power supply terminal VDD, and a drain.Transistor 28 has gate for receiving reference voltage Vref, a sourceconnected to VDD, and drain connected to the drain of transistor 26.Transistor 30 has a gate and drain connected to the drains oftransistors 26 and 28 and a source connected to a negative power supplyterminal, ground in this example. Transistor 32 has a gate and drainconnected to the drains of transistors 26 and 28 and a source connectedto ground. Transistors 26 and 28, 30, and 32 form a bias circuit inwhich a bias signal Vbias is provided at a bias node 49 at theconnections of the drains of transistors 26, 28, 30, and 32.

Transistor 36 has a gate for receiving bit signal Vbit, a sourceconnected to a positive power supply terminal VDD, and a drain.Transistor 38 has a gate connected to the drain of transistor 30, drainconnected to the drain of transistor 36, and a source connected toground. Transistor 40 has a gate for receiving a voltage reference Vref,a source connected to VDD, and a drain. Transistor 42 has a drainconnected to the drain of transistor 40, a gate connected to the drainof transistor 30, and a source connected to ground. Transistors 36 and38 form one output stage, and transistors 40, and 42 form another outputstage of comparator 18 in which the true output is at the drains oftransistors 40 and 42 and is shown as output Vo. The complementaryoutput is at the drains of transistors 36 and 38 and is shown as outputbar Vob.

Latch 19 has a first input for receiving output Vo, a second input forreceiving output bar Vob, and an output for providing a data outputsignal Do.

In operation a memory cell is selected for reading. In this example,memory cell 20 is selected. Preamplifier 16 provides a current throughmemory cell 20 and converts that to a voltage which is provided as bitsignal Vbit. Similarly, preamplifier 16 provides current through memorycells 22 and 24, takes an average of that current, and converts that toa voltage which is provided as reference voltage Vref. This is a commonoperation for a first stage in sensing the logic state of MRAM cells.

Transistor 26 receives a bit signal Vbit and provides a correspondingcurrent to transistors 30 and 32 which are diode connected. Similarlytransistor 28 receives reference voltage Vref and provides acorresponding current to transistors 30 and 32. With transistors 30 and32 diode connected, the current through transistors 30 and 32 ismirrored to transistors 38 and 42 by bias signal Vbias to establish abias current for transistors 38 and 42. This current through transistors30 and 32, represented by bias signal Vbias, is the sum of currentsthrough transistors 26 and 28. Transistors 30 and 32 are preferablychosen to be the same size so that the current through one of them isequal to the average of the currents through transistors 26 and 28. Thusit is the average current of transistors 26 and 28 that is mirrored bytransistors 30 and 32.

The bias current that is established for transistor 38 is the ratio ofthe size of transistor 38 to the size of one of transistors 30 and 32times the average current of transistors 26 and 28. The bias currentthat is established for transistor 42 is the ratio of the size oftransistor 42 to the size of one of transistors 30 and 32 times theaverage current of transistors 26 and 28. Establishing a bias currentfor transistors 38 and 42 is not necessarily a current that is actuallyflowing but is the current that would flow if the transistors were insaturation. One of transistors 38 and 42 will not be in saturation whensensing has occurred. Transistors 26 and 28 are preferably the samesize. Transistors 38 and 42 are preferably the same size. Transistors 36and 40 are preferably the same size. The ratio of the transistors 26 totransistor 30 is preferably the same as the ratio of transistor 36 totransistor 38. The effect is that preferably the P to N channel ratio ofthe bias circuit is the same as the P to N channel ratio of the outputstages. This ratio is preferable to provide a bias point atapproximately half of the power supply voltage.

Transistor 38 may have a size that is a multiple of the size oftransistor 30, so also transistor 36 would have a size that is amultiple of the size of transistor 26. Setting a multiple greater thanone in these cases of the size ratio between the output circuit,transistors 36 and 38, and the bias circuit, transistors 26 and 30, hasthe effect of reducing loading of the bias circuit on the input signal,Vbit. The result is a stronger Vbit so that the output circuit providesa stronger output.

Transistor 36 receives bit signal Vbit while transistor 40 receivesreference voltage Vref. For the case where bit signal Vbit isrepresentative of a logic low of memory cell 20, bit signal Vbit will bea lower voltage than reference voltage Vref. Bias voltage Vbias willestablish a bias current in transistors 38 and 42 based on the averageof the current representative of a logic low and the reference.Transistor 36 will supply more current than the bias current intransistor 38 so that output Vob will rise. Transistor 40 will supplyless current than the bias current so that output signal Vo will fall.Output voltages Vo and Vob will thus produce true and complementarysignals that latch 19 can readily sense and latch and provide dataoutput signal Do as a logic low. For the case where bit signal Vbit isrepresentative of a logic high of memory cell 20, bit signal Vbit willbe a higher voltage than reference voltage Vref. Bias voltage Vbias willestablish a bias current in transistors 38 and 42 based on the averageof the current representative of a logic high and the reference.Transistor 36 will supply less current than the bias current intransistor 38 so that output Vob will fall. Transistor 40 will supplymore current than the bias current so that output signal Vo will rise.Output voltages Vo and Vob will thus produce true and complementarysignals that latch 19 can readily sense and latch and provide dataoutput signal Do as a logic high.

Prior to performing the read operation, transmission gates 44 and 46equalize the drains of the transistors of the comparator and outputstage at a voltage V2 supplied by transmission gate 48. Transmissiongate 48 is conductive in response to precharge signal PQ which is activeprior to a read while transmission gates 44 and 46 are conductive inresponse to equalization signal EQ being active. Voltage V2 isapproximately the level of reference voltage Vref. Precharge signal PQis made inactive and memory cell 20 is accessed. After sufficient timefor bit signal Vbit to become active, signal EQ becomes inactive toallow bias sense amplifier 18 to sense the logic state of bit signalVbit.

A benefit of this approach of the bias being an average of the referenceand the input signal is that the adverse effect of a common mode offsetin the reference and input signal is greatly diminished. Also because ofthe averaging of the bias current, there is minimal adverse impact ofmismatched transistors in the bias circuit.

Various other changes and modifications to the embodiments herein chosenfor purposes of illustration will readily occur to those skilled in theart. For example, the operation was described for a single memory cellbut other memory cells could also be sensed by similar sense amplifiersat the same time. Transistors 30 and 32 were shown for dividing currentto provide an average but this could be achieved with just onetransistor that is twice as big. Size of a transistor refers to thechannel width to channel length ratio. Although there are believed to bebenefits in having the P channel to N channel ratios being as described,there may be other possibilities for these ratios that may bebeneficial. To the extent that such modifications and variations do notdepart from the spirit of the invention, they are intended to beincluded within the scope thereof which is assessed only by a fairinterpretation of the following claims.

1. In a memory having a pre-amplifier for generating at least one outputsignal and at least one reference signal, the memory further comprisingat least one comparator for comparing one of the at least one outputsignal to one of the at least one reference signal, the at least onecomparator comprising: a bias stage comprising: a first transistor of afirst conductivity type having a first current terminal coupled to afirst supply, a control terminal coupled to the one of the at least oneoutput signal, and a second current terminal, a second transistor of thefirst conductivity type having a first current terminal coupled to thefirst supply, a control terminal coupled to the one of the at least onereference signal, and a second current terminal coupled to the secondcurrent terminal of the first transistor forming a biasing node, and athird transistor of a second conductivity type having a first currentterminal coupled to the biasing node, a control terminal coupled to thebiasing node, and a second current terminal coupled to a second supply,wherein the first supply is different from the second supply; and afirst output stage coupled to the biasing node and a second output stagecoupled to the biasing node.
 2. The memory of claim 1, the first outputstage comprising: a fourth transistor of the first conductivity typehaving a first current terminal coupled to the first supply, a controlterminal coupled to the one of the at least one output signal, a secondcurrent terminal; and a fifth transistor of the second conductivity typehaving a first current terminal coupled to the second current terminalof the fourth transistor, a control terminal coupled to the biasingnode, and a second current terminal coupled to the second supply.
 3. Thememory of claim 2, the second output stage comprising: a sixthtransistor of the first conductivity type having a first currentterminal coupled to the first supply, a control terminal coupled to theone of the at least one reference signal, a second current terminal; anda seventh transistor of the second conductivity type having a firstcurrent terminal coupled to the second current terminal of the sixthtransistor, a control terminal coupled to the biasing node, and a secondcurrent terminal coupled to the second supply.
 4. The memory of claim 3further characterized by for equalizing a voltage at the second currentterminal of the fourth transistor to a voltage at the second currentterminal of the sixth transistor, in response to an equalization signal.5. The memory of claim 3, further characterized by for pre-charging avoltage at the biasing node, a voltage at the second current terminal ofthe fourth transistor to a voltage at the second current terminal of thesixth transistor, in response to a pre-charging signal.
 6. The memory ofclaim 3, further characterized by a latch coupled to the second currentterminal of the fourth transistor and the second current terminal of thesixth transistor, the latch generating a data output signal.
 7. Thememory of claim 1, wherein the bias stage is further characterized by aneighth transistor of the second conductivity type having a first currentterminal coupled to the biasing node, a control terminal coupled to thebiasing node, and a second current terminal coupled to the secondsupply.
 8. The memory of claim 2, further characterized by the fourthtransistor and the first transistor having a first gain ratio and thefifth transistor and the third transistor having a second gain ratio,such that the first gain ratio is substantially the same as the secondgain ratio.
 9. The memory of claim 7 further characterized by the sixthtransistor and the second transistor having a third gain ratio and theseventh transistor and the eighth transistor having a fourth gain ratio,such that the third and fourth gain ratios are substantially the same asthe first gain ratio.
 10. In a circuit having a pre-amplifier forgenerating an output signal and a reference signal, a method comprising:generating a bias signal as an average of the output signal and thereference signal; generating a first comparator output signal bycomparing the output signal and the bias signal; and generating a secondcomparator output signal by comparing the reference signal and the biassignal.
 11. The method of claim 10 further characterized by equalizingthe first comparator output signal and the second comparator outputsignal, in response to an equalization signal.
 12. The method of claim10 further characterized by pre-charging the first comparator outputsignal, the second comparator output signal, and the bias signal, inresponse to a pre-charging signal.
 13. The memory of claim 4 furthercharacterized by for pre-charging a voltage at the biasing node, avoltage at the second current terminal of the fourth transistor to avoltage at the second current terminal of the sixth transistor, inresponse to a pre-charging signal.
 14. The memory of claim 4 furthercharacterized by a latch coupled to the second current terminal of thefourth transistor and the second current terminal of the sixthtransistor, the latch generating a data output signal.
 15. The memory ofclaim 2 wherein the bias stage is further characterized by an eighthtransistor of the second conductivity type having a first currentterminal coupled to the biasing node, a control terminal coupled to thebiasing node, and a second current terminal coupled to the secondsupply.
 16. The memory of claim 3 further characterized by the fourthtransistor and the first transistor having a first gain ratio and thefifth transistor and the third transistor having a second gain ratio,such that the first gain ratio is substantially the same as the secondgain ratio.
 17. The memory of claim 8 further characterized by the sixthtransistor and the second transistor having a third gain ratio and theseventh transistor and the eighth transistor having a fourth gain ratio,such that the third and fourth gain ratios are substantially the same asthe first gain ratio.
 18. The method of claim 11 further characterizedby pre-charging the first comparator output signal, the secondcomparator output signal, and the bias signal, in response to apre-charging signal.